SIMM
SIMM
單列直插式內存模塊(single in-line memory module,縮寫SIMM)是一種在20世紀80年代初到90年代後期在計算機中使用的包含隨機存取存儲器的內存模塊。它與現今最常見的雙列直插式內存模塊(DIMM)不同之處在於,SIMM模塊兩側的觸點是冗餘的。SIMM根據JEDEC JESD-21C標準進行了標準化。
大多數早期PC主板(基於8088的PC、XT、和早期AT)採用面向DRAM的插座式雙列直插封裝(DIP)晶元。隨著計算機內存容量的增長,內存模塊被用於節約主板空間和簡化內存擴展。相比插入八、九個DIP晶元,只需插入一個內存模塊就能增加計算機的內存。
30針SIMM有12個地址行,它可以提供總計24個地址比特。對於8位數據寬度,則奇偶校驗和非奇偶校驗模塊的絕對最大容量為16MB(額外的冗餘比特晶元通常對可用容量無貢獻)。
30針SIMM內存模塊 | |||||
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針腳 # | 名稱 | 信號說明 | 針腳 # | 名稱 | 信號說明 |
1 | V | +5 VDC | 16 | DQ4 | Data 4 |
2 | /CAS | Column Address Strobe | 17 | A8 | Address 8 |
3 | DQ0 | Data0 | 18 | A9 | Address 9 |
4 | A0 | Address0 | 19 | A10 | Address 10 |
5 | A1 | Address1 | 20 | DQ5 | Data 5 |
6 | DQ1 | Data1 | 21 | /WE | Write Enable |
7 | A2 | Address2 | 22 | V | Ground |
8 | A3 | Address3 | 23 | DQ6 | Data 6 |
9 | V | Ground | 24 | A11 | Address 11 |
10 | DQ2 | Data2 | 25 | DQ7 | Data 7 |
11 | A4 | Address4 | 26 | QP | Data parity out |
12 | A5 | Address5 | 27 | /RAS | Row Address Strobe |
13 | DQ3 | Data3 | 28 | /CASP | Parity Column Address Strobe |
14 | A6 | Address6 | 29 | DP | Data parity in |
15 | A7 | Address7 | 30 | V | +5 VDC |
針腳26、28和29在非奇偶校驗SIMM上不連通。
標準大小:1MB、2MB、4MB、8MB、16MB、32MB、64MB、128MB(標準也定義了有額外地址行且最高2GB的3.3 V模塊)
採用12個地址線,可以提供總計24個地址比特,兩個晶元Rank,以及32位數據輸出,絕對最大容量為2=128 MB。
5 V 72針SIMM內存模塊 | |||||
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針腳 # | 名稱 | 信號說明 | 針腳 # | 名稱 | 信號說明 |
1 | V | Ground | 37 | MDP1 | Data Parity 1(MD8..15) |
2 | MD0 | Data0 | 38 | MDP3 | Data Parity 3 (MD24..31) |
3 | MD16 | Data16 | 39 | V | Ground |
4 | MD1 | Data1 | 40 | /CAS0 | Column Address Strobe 0 |
5 | MD17 | Data17 | 41 | /CAS2 | Column Address Strobe 2 |
6 | MD2 | Data2 | 42 | /CAS3 | Column Address Strobe 3 |
7 | MD18 | Data18 | 43 | /CAS1 | Column Address Strobe 1 |
8 | MD3 | Data3 | 44 | /RAS0 | Row Address Strobe 0 |
9 | MD19 | Data19 | 45 | /RAS1 | Row Address Strobe 1 |
10 | V | +5 VDC | 46 | NC | Not Connected |
11 | NU [PD5] | Not Used [Presence Detect 5 (3v3)] | 47 | /WE | Read/Write Enable |
12 | MA0 | Address 0 | 48 | NC [/ECC] | Not Connected [ECC presence (if grounded) (3v3)] |
13 | MA1 | Address 1 | 49 | MD8 | Data 8 |
14 | MA2 | Address 2 | 50 | MD24 | Data 24 |
15 | MA3 | Address 3 | 51 | MD9 | Data 9 |
16 | MA4 | Address 4 | 52 | MD25 | Data 25 |
17 | MA5 | Address 5 | 53 | MD10 | Data 10 |
18 | MA6 | Address 6 | 54 | MD26 | Data 26 |
19 | MA10 | Address10 | 55 | MD11 | Data 11 |
20 | MD4 | Data4 | 56 | MD27 | Data 27 |
21 | MD20 | Data20 | 57 | MD12 | Data 12 |
22 | MD5 | Data5 | 58 | MD28 | Data 28 |
23 | MD21 | Data21 | 59 | V | +5 VDC |
24 | MD6 | Data6 | 60 | MD29 | Data 29 |
25 | MD22 | Data22 | 61 | MD13 | Data 13 |
26 | MD7 | Data7 | 62 | MD30 | Data 30 |
27 | MD23 | Data23 | 63 | MD14 | Data 14 |
28 | MA7 | Address7 | 64 | MD31 | Data 31 |
29 | MA11 | Address11 | 65 | MD15 | Data 15 |
30 | V | +5 VDC | 66 | NC [/EDO] | Not Connected [EDO presence (if grounded) (3v3)] |
31 | MA8 | Address 8 | 67 | PD1 | Presence Detect 1 |
32 | MA9 | Address 9 | 68 | PD2 | Presence Detect 2 |
33 | /RAS3 | Row Address Strobe 3 | 69 | PD3 | Presence Detect 3 |
34 | /RAS2 | Row Address Strobe 2 | 70 | PD4 | Presence Detect 4 |
35 | MDP2 | Data Parity 2 (MD16..23) | 71 | NC [PD (ref)] | Not Connected [Presence Detect (ref) (3v3)] |
36 | MDP0 | Data Parity 0 (MD0..7) | 72 | V | Ground |
針腳35、36、37和38在非奇偶校驗SIMM上不連通。
/RAS1和/RAS3僅在雙rank SIMM上使用:即2、8、32和128MB。
這些線路僅在3.3V模塊上定義。
存在檢測信號詳見JEDEC標準。
Great Valley Products用於CommodoreAmiga的多款CPU卡使用特殊的64針SIMM(32位寬,1、4或16MB,60 ns)。
蘋果公司Macintosh IIfx計算機中使用雙埠64針SIMM,這允許重疊的讀/寫周期(1、4、8、16 MB,80 ns)。
5V 64針Mac IIfx SIMM內存模塊 | |||||
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針腳 # | 名稱 | 信號說明 | 針腳 # | 名稱 | 信號說明 |
1 | GND | Ground | 33 | Q4 | Data output bus, bit 4 |
2 | NC | Not connected | 34 | /W4 | Write-enable input for RAM IC 4 |
3 | +5V | +5volts | 35 | A8 | Address bus, bit 8 |
4 | +5V | +5volts | 36 | NC | Not connected |
5 | /CAS | Column address strobe | 37 | A9 | Address bus, bit 9 |
6 | D0 | Data input bus, bit 0 | 38 | A10 | Address bus, bit 10 |
7 | Q0 | Data output bus, bit 0 | 39 | A11 | Address bus, bit 11 |
8 | /W0 | Write-enable input for RAM IC 0 | 40 | D5 | Data input bus, bit 5 |
9 | A0 | Address bus, bit 0 | 41 | Q5 | Data output bus, bit 5 |
10 | NC | Not connected | 42 | /W5 | Write-enable input for RAM IC 5 |
11 | A1 | Address bus, bit 1 | 43 | NC | Not connected |
12 | D1 | Data input bus, bit 1 | 44 | NC | Not connected |
13 | Q1 | Data output bus, bit 1 | 45 | GND | Ground |
14 | /W1 | Write-enable input for RAM IC 1 | 46 | D6 | Data input bus, bit 6 |
15 | A2 | Address bus, bit 2 | 47 | Q6 | Data output bus, bit 6 |
16 | NC | Not connected | 48 | /W6 | Write-enable input for RAM IC 6 |
17 | A3 | Address bus, bit 3 | 49 | NC | Not connected |
18 | GND | Ground | 50 | D7 | Data input bus, bit 7 |
19 | GND | Ground | 51 | Q7 | Data output bus, bit 7 |
20 | D2 | Data input bus, bit 2 | 52 | /W7 | Write-enable input for RAM IC 7 |
21 | Q2 | Data output bus, bit 2 | 53 | /QB | Reserved (parity) |
22 | /W2 | Write-enable input for RAM IC 2 | 54 | NC | Not connected |
23 | A4 | Address bus, bit 4 | 55 | /RAS | Row address strobe |
24 | NC | Not connected | 56 | NC | Not connected |
25 | A5 | Address bus, bit 5 | 57 | NC | Not connected |
26 | D3 | Data input bus, bit 3 | 58 | Q | Parity-check output |
27 | Q3 | Data output bus, bit 3 | 59 | /WWP | Write wrong parity |
28 | /W3 | Write-enable input for RAM IC 3 | 60 | PDCI | Parity daisy-chain input |
29 | A6 | Address bus, bit 6 | 61 | +5V | +5volts |
30 | NC | Not connected | 62 | +5V | +5volts |
31 | A7 | Address bus, bit 7 | 63 | PDCO | Parity daisy-chain output |
32 | D4 | Data input bus, bit 4 | 64 | GND | Ground |
72針SIMM採用非標準的存在檢測(PD)連接。
• 雙列直插封裝(DIP)
• 雙列直插封裝(SIP)
• Zig-zag in-line package(ZIP)
• 雙列直插式內存模塊(DIMM)