m68k

m68k是摩托羅拉的68000型cpu

學習和研究彙編語言/IDA/Linux時，您可能會需要相關知識.

以下是m68k的彙編指令集

MotoROLa 68000 Instruction Set.

Condition Codes

assemblerData

Instruction Description Syntax Size X N Z V C

ABCD Add BCD with extend Dx,Dy B-- * U * U *

-(Ax),-(Ay)

ADD ADD binary Dn, BWL * * * * *

addaADD binary to An ,An -WL - - - - -

ADDI ADD Immediate #x, BWL * * * * *

ADDQ ADD 3-bit immediate #<1-8>, BWL * * * * *

ADDX ADD eXtended Dy,Dx BWL * * * * *

-(Ay),-(Ax)

AND Bit-wise AND ,Dn BWL - * * 0 0

Dn,

ANDiBit-wise AND with Immediate #, BWL - * * 0 0

ASL Arithmetic Shift Left #<1-8>,Dy BWL * * * * *

Dx,Dy

ASR Arithmetic Shift Right ... BWL * * * * *

bccConditional Branch Bcc.S BW- - - - - -

Bcc.W

BCHG Test a Bit and CHanGe Dn, B-L - - * - -

#,

BCLR Test a Bit and CLeaR ... B-L - - * - -

BSET Test a Bit and SET ... B-L - - * - -

BSR Branch to subroutine BSR.S BW- - - - - -

BSR.W

BTST Bit TeST Dn, B-L - - * - -

#,

CHKCHecK Dn Against Bounds ,Dn -W- - * U U U

CLR CLeaR BWL - 0 1 0 0

CMP CoMPare ,Dn BWL - * * * *

CMPA CoMPare Address ,An -WL - * * * *

CMPICoMPare Immediate #, BWL - * * * *

cmpmCoMPare Memory (Ay)+,(Ax)+ BWL - * * * *

DBCCloopingInstruction DBcc Dn, -W- - - - - -

DIVS DIVide Signed ,Dn -W- - * * * 0

DIVU DIVide Unsigned ,Dn -W- - * * * 0

EORExclusive OR Dn, BWL - * * 0 0

EORI Exclusive OR Immediate #, BWL - * * 0 0

EXG Exchange any two registers Rx,Ry --L - - - - -

EXT Sign EXTend Dn -WL - * * 0 0

ILLEGAL ILLEGAL-Instruction Exception ILLEGAL - - - - -

JMP JuMP to Affective Address - - - - -

JSR Jump to SubRoutine - - - - -

LEA Load Effective Address ,An --L - - - - -

LINK allocate Stack Frame An,# - - - - -

LSLLogical Shift Left Dx,Dy BWL * * * 0 *

#<1-8>,Dy

LSR Logical Shift Right ... BWL * * * 0 *

MOVE Between Effective Addresses , BWL - * * 0 0

MOVE To CCR ,CCR -W- I I I I I

MOVE To SR ,SR -W- I I I I I

MOVE From SR SR, -W- - - - - -

MOVE USP to/from Address Register USP,An --L - - - - -

An,USP

MOVEA MOVE Address ,An -WL - - - - -

MOVEM MOVE Multiple , -WL - - - - -

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MOVEP MOVE Peripheral Dn,x(An) -WL - - - - -

x(An),Dn

MOVEQ MOVE 8-bit immediate #<-128.+127>,Dn --L - * * 0 0

MULS MULtiply Signed ,Dn -W- - * * 0 0

MULU MULtiply Unsigned ,Dn -W- - * * 0 0

NBCD Negate BCD B-- * U * U *

NEG NEGate BWL * * * * *

NEGX NEGate with eXtend BWL * * * * *

NOP No OPeration NOP - - - - -

NOT Form one's complement BWL - * * 0 0

OR Bit-wise OR ,Dn BWL - * * 0 0

Dn,

ORI Bit-wise OR with Immediate #, BWL - * * 0 0

PEA Push Effective Address --L - - - - -

RESET RESET all external devices RESET - - - - -

ROL ROtate Left #<1-8>,Dy BWL - * * 0 *

Dx,Dy

RORROtate Right ... BWL - * * 0 *

ROXL ROtate Left with eXtend ... BWL * * * 0 *

ROXR ROtate Right with eXtend ... BWL * * * 0 *

RTE ReTurn from Exception RTE I I I I I

RTR ReTurn and Restore RTR I I I I I

RTS ReTurn from Subroutine RTS - - - - -

SBCD Subtract BCD with eXtend Dx,Dy B-- * U * U *

-(Ax),-(Ay)

Scc Set to -1 if True, 0 if False B-- - - - - -

STOP Enable & wait for interrupts # I I I I I

SUB SUBtract binary Dn, BWL * * * * *

SUBA SUBtract binary from An ,An -WL - - - - -

SUBI SUBtract Immediate #x, BWL * * * * *

SUBQ SUBtract 3-bit immediate #, BWL * * * * *

SUBX SUBtract eXtended Dy,Dx BWL * * * * *

-(Ay),-(Ax)

SWAP SWAP words of Dn Dn -W- - * * 0 0

TAS Test & Set MSB & Set N/Z-bits B-- - * * 0 0

TRAP Execute TRAP Exception # - - - - -

TRAPV TRAPV Exception if V-bit Set TRAPV - - - - -

TST TeST for negative or zero BWL - * * 0 0

UNLK Deallocate Stack Frame An - - - - -

Symbol Meaning

* Set according to result of operation

- Not affected

0 Cleared

1 Set

U Outcome (state after operation) undefined

I Set by immediate data

... Same as previous instruction

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Addressing Modes Syntax

Data Register Direct Dn

Address Register Direct An

Address Register Indirect (An)

Address Register Indirect with Post-increment (An)+

Address Register Indirect with Pre-decrement -(An)

Address Register Indirect with Displacement w(An)

Address Register Indirect with Index b(An,Rx)

Absolute Short w

Absolute Long l

Program Counter with Displacement w(PC)

Program Counter with Index b(PC,Rx)

Immediate #x

Status Register SR

Condition Code Register CCR

Legend

------

Dn Data Register (n is 0-7)

An Address Register (n is 0-7)

b 08-bit constant

w 16-bit constant

l 32-bit constant

x 8-, 16-, 32-bit constant

Rx Index Register Specification, one of:

Dn.W Low 16 bits of Data Register

Dn.L All 32 bits of Data Register

An.W Low 16 bits of Address Register

An.L All 32 bits of Address Register

Condition Codes for Bcc, DBcc and Scc Instructions.

Condition Codes set after CMP D0,D1 Instruction.

Relationship Unsigned Signed

D1 < D0 CS - Carry Bit Set LT - Less Than

D1 <= D0 LS - Lower or Same LE - Less than or Equal

D1 = D0 EQ - Equal (Z-bit Set) EQ - Equal (Z-bit Set)

D1 != D0 NE - Not Equal (Z-bit Clear) NE - Not Equal (Z-bit Clear)

D1 > D0 HI - HIgher than GT - Greater Than

D1 >= D0 CC - Carry Bit Clear GE - Greater than or Equal

PL - PLus (N-bit Clear) MI - Minus (N-bit Set)

VC - V-bit Clear (No Overflow) VS - V-bit Set (Overflow)

RA - BRanch Always

DBcc Only - F - Never Terminate (DBRA is an alternate to DBF)

T - Always Terminate

Scc Only - SF - Never Set

ST - Always Set

Parts from "Programming the 68000" by Steve Williams. (c) 1985 Sybex Inc.

Parts from BYTE Magazine article.

Compiled by Diego Barros. e-mail : [email protected]

Revision 2.1 22 May, 1994

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