AHDL

AHDL

Altera 公司的用於描述數字邏輯的硬體描述語言。類似VHDL和Verilog HDL，用於對數字邏輯電路進行建模。

目錄

1內容描述 2出處引用

內容描述

1. Altera Hardware Description Language

例子

% a simple AHDL up counter, released to public domain 13 November 2006 %

% [block quotations achieved with percent sign] %

% like c, ahdl functions must be prototyped %

% PROTOTYPE:

FUNCTION COUNTER (CLK)

RETURNS (CNTOUT[7..0]); %

% function declaration, where inputs, outputs, andbidirectional pins are declared %

% also like c, square brakets indicate an array %

SUBDESIGN COUNTER

(

CLK :INPUT;

CNTOUT[7..0] :OUTPUT;

)

% variables can be anything from flip-flops (as in this case),tri-state buffers, state machines, to user defined functions %

VARIABLE

TIMER[7..0]: DFF;

% as with all hardware description languages, think of this less as an algorithm and more as wiring nodes together %

BEGIN

DEFAULTS

TIMER[].prn = VCC; % this takes care of d-ff resets %

TIMER[].clrn = VCC;

END DEFAULTS;

TIMER[].d = TIMER[].q + H"1";

END;

2. Analog Hardware Description Language

模擬硬體描述語言。

出處引用

Modeling with an Analog Hardware Description Language (The International Series in Engineering and Computer Science) (Hardcover)

by H. Alan Mantooth, Mike F. Fiegenbaum

目錄